Pattern matching in bioinformatics computing

Pattern matching is a difficult task in bioinformatics. Pattern matching involves finding one or more matches quickly from large databases by employing the use of minimum hardware. Pattern matching finds wide applications in bioinformatics. Some of the applications are in the construction of controlled vocabularies, data mining, genome sequencing, functional proteomics, functional genomics, natural language processing, homologous gene identification, homologous protein identification, neural network based structure classifiers, nucleotide sequence alignment, protein sequence alignment, rule-based structure classifiers and protein structure prediction. The major task in the field of pattern matching is the sequence alignment. There are three categories here- pairwise sequence alignment, local versus global alignment and multiple sequence alignment. In pairwise sequence alignment, natching of two sequences,, one pair of elements at a time is carried out. The different computational methods used for sequence alignment are Bayesian methods, dot matrix method, dynamic programming method, genetic algorithms method, Hidden Markov models method, neural networks method, word based methods and scoring matrices method.

Pipelining and caching of CPU

CPU stands for central processing unit which is the core part of a computer. CPU performance is treated as better if it can execute instructions fast. The two factors which influence CPU performance are pipelining and caching. Latest processor design supports parallel program executions with the help of pipelined machines. Pipelining design increases the efficiency of the CPU but only till contents flow smoothly. If particular sequences of instructions disrupt the flow of information in the pipeline, it will result in the slowing down of the CPU operation. The three stages of ARM7 processor pipeline are fetch, decode and execute.  Each of these stages requires one clock cycle for typical instructions. A normal instruction set require three cycles for the complete execution of the task and this is called latency of instruction execution. C55x processor includes a seven stage pipeline. These seven stages are fetch, decode, address, access1, access2, read stage and execute. Timing characteristics of a pipelined RISC machine is more regular and most of the instructions that do not have pipeline hazards display the same latency. Caches which influence CPU performance are usually invisible in a programming model. Introduction of caches reduces the memory access time. If caches are not provided, a processor has to spend more time for accessing a memory location and this time is referred as cache miss penalty.  

Optical fiber sensor

Measurement of pressure, flow rate, liquid level, temperature etc. can be carried out by using optical fiber sensors. The fact that the temperature and pressure changes bring a change in the effective length of the fiber is employed here since the change in length can produce a small phase change.  A long fiber is capable of magnifying this small phase change into a measurable amount. The major components of an optical fiber sensor are optical source, feed fiber, modulator, return fiber and optical detector. Laser is used as an optical source. Feed fiber takes the laser light towards modulator. Modulation is being done here in five properties namely optical intensity, phase, wavelength, spectral distribution and polarization. Some examples of optical fiber sensors are phase fiber sensor, polarization fiber sensor, ring interferometer with multiturn fiber coil, fiber optical fluid level detector, optical fiber flow sensor, optical displacement sensor, optical displacement moiré fringe modulation sensor, micro bend optical fiber sensor, single mode optical fiber sensor, fluoroptic temperature sensor, photo elastic pressure sensor and laser Doppler optical fiber velocimeter.

CPU scheduling policies

A scheduling policy characterizes how CPU processes are selected and promoted from the ready state to the running state. Every operating system operates by governing a well defined scheduling policy.  Choice of scheduling policy is very important to tune timing requirements and fixing the required horsepower of CPU for the superior system functioning. Schedulability is a query of existence of a schedule of execution for the processes in a system that satisfies all their timing requirements. For this either construct a schedule to show schedulability or eliminate some processes terming unschedulable using some techniques. CPU utilization, one of the key metrics in the evaluation of scheduling policy should not cross 100%. Hyperperiod which is the LCM of the periods of all the CPU processes is considered during CPU utilization evaluation. Cyclostatic which is also known as time division multiple access scheduling is a simple scheduling policy. Here whole schedule is divided into equal-sized time slots over an interval equal to the length of the hyperperiod. Round robin is another scheduling policy which uses the same hyperperiod as cyclostatic but here when process does not have any useful work to do, round-robin scheduler moves on to the next process in order to fill the time slot with useful work.

Bus-based computer systems

Bus-based computer systems can be created by using good choice of microprocessors, input/output devices and appropriate memory components. CPU bus is a set up used for the interconnection of these constituent components. Thus through bus, CPU communicates with memory and input/output devices. A bus is a collection of wires and defined by a protocol. This protocol allows smooth communication between CPU and memory/input/output devices. Bus provides an effective and excellent interface to memory. The basic building block of bus protocol is four-cycle handshake. This block ensures that when two devices want to communicate, one is ready to transmit and the other is ready to receive. Here two wires are used for this purpose. These wires are named as ‘enq’ meaning enquiry and ‘ack’ meaning acknowledge. Some additional wires are also used during data transmission. In the first cycle, the first device raises its output to signal an enquiry. This makes second device ready for reception of data. In the second cycle, second device raises its output to signal acknowledgement. Now both the devices are ready for transmission and reception. In the third cycle, second device lowers its output and signals the complete reception of data. In the fourth and last cycle, first device lowers its output.

Flip-flop circuits

The present era, the era of digital devices mainly concerned about storage technology. Storage of data and processing of data are the two main functions that to be attended in digital technology. Binary counting devices require digital devices with two stable states. These devices are capable of undergoing a change from one state to another by the application of a trigger pulse to one of its inputs. A flip-flop is an ideal circuit with two stable states. It is capable of storing a signal like a ‘memory’ until new signal is applied to the circuit. Different types of flip-flops exist in the market. They are Set-Reset (SR) flip-flop, JK master slave flip-flop and D-flip-flop. SR flip-flops have two inputs and two outputs. Either NOR gates or NAND gates are used for the construction of SR flip-flop. An emitter-coupled bistable multivibrator can be used as an SR flip-flop. Master slave principle is used in JK master slave flip-flops. The main application of JK master slave flip-flops are in complex counters. Only one input is provided in D-flip-flops and they are widely used in shift registers and sequential logic circuits.