Pipelining and caching of CPU

CPU stands for central processing unit which is the core part of a computer. CPU performance is treated as better if it can execute instructions fast. The two factors which influence CPU performance are pipelining and caching. Latest processor design supports parallel program executions with the help of pipelined machines. Pipelining design increases the efficiency of the CPU but only till contents flow smoothly. If particular sequences of instructions disrupt the flow of information in the pipeline, it will result in the slowing down of the CPU operation. The three stages of ARM7 processor pipeline are fetch, decode and execute.  Each of these stages requires one clock cycle for typical instructions. A normal instruction set require three cycles for the complete execution of the task and this is called latency of instruction execution. C55x processor includes a seven stage pipeline. These seven stages are fetch, decode, address, access1, access2, read stage and execute. Timing characteristics of a pipelined RISC machine is more regular and most of the instructions that do not have pipeline hazards display the same latency. Caches which influence CPU performance are usually invisible in a programming model. Introduction of caches reduces the memory access time. If caches are not provided, a processor has to spend more time for accessing a memory location and this time is referred as cache miss penalty.