Sequential and combinational
logic elements are basic components of a digital system. During designing of a
circuit, first step is to convert word description to algorithmic state machine
chart. After this, state synthesis table is prepared. In flip-flop based
circuits, these tables are used to generate design equations through Karnaugh
Map. These design equations helps to develop the final circuit diagram. State
machine design model is of two types- Moore
model and Mealy model. If secondary outputs or memory values generates primary
outputs, then the model is termed as Moore
model. In Mealy model, primary inputs combine with memory elements to generate
circuit output. A sequential logic circuit is a synchronous clock-triggered
circuit. This can be designed in two ways. In the first model, output depends
only on present state and not on input (Moore
model). The other model (Mealy model) output is derived from present state as
well as input. Since Mealy model requires less number of states, hardware
requirement is minimum. After fixing any one of these models, next step is to
fix the algorithmic state machine chart. After fixing this chart, state
synthesis table has to be developed. The final stage includes usage of design
equations and circuit diagram and implementation using read only memory.
