CPU scheduling policies

A scheduling policy characterizes how CPU processes are selected and promoted from the ready state to the running state. Every operating system operates by governing a well defined scheduling policy.  Choice of scheduling policy is very important to tune timing requirements and fixing the required horsepower of CPU for the superior system functioning. Schedulability is a query of existence of a schedule of execution for the processes in a system that satisfies all their timing requirements. For this either construct a schedule to show schedulability or eliminate some processes terming unschedulable using some techniques. CPU utilization, one of the key metrics in the evaluation of scheduling policy should not cross 100%. Hyperperiod which is the LCM of the periods of all the CPU processes is considered during CPU utilization evaluation. Cyclostatic which is also known as time division multiple access scheduling is a simple scheduling policy. Here whole schedule is divided into equal-sized time slots over an interval equal to the length of the hyperperiod. Round robin is another scheduling policy which uses the same hyperperiod as cyclostatic but here when process does not have any useful work to do, round-robin scheduler moves on to the next process in order to fill the time slot with useful work.

Bus-based computer systems

Bus-based computer systems can be created by using good choice of microprocessors, input/output devices and appropriate memory components. CPU bus is a set up used for the interconnection of these constituent components. Thus through bus, CPU communicates with memory and input/output devices. A bus is a collection of wires and defined by a protocol. This protocol allows smooth communication between CPU and memory/input/output devices. Bus provides an effective and excellent interface to memory. The basic building block of bus protocol is four-cycle handshake. This block ensures that when two devices want to communicate, one is ready to transmit and the other is ready to receive. Here two wires are used for this purpose. These wires are named as ‘enq’ meaning enquiry and ‘ack’ meaning acknowledge. Some additional wires are also used during data transmission. In the first cycle, the first device raises its output to signal an enquiry. This makes second device ready for reception of data. In the second cycle, second device raises its output to signal acknowledgement. Now both the devices are ready for transmission and reception. In the third cycle, second device lowers its output and signals the complete reception of data. In the fourth and last cycle, first device lowers its output.